让内网的vsftpd支持被动模式
2007年6月3日
存档
2007年6月 的存档
Verilog HDL General Guidelines
2007年6月1日
1. Use ‘=’ for combinational assignments and ‘<=' registered assignments.
2. If you are describing combinational logic in an always block:
(1)Make sure all input signals are in event list.
(2)Make sure a value is assigned to an output signal on every path through block.
3. Make the language work for you.
Use built in. E.g. +, -, <<, >>, case …
4. Think of hardware always !
5. Synchronous design.
6. Use some useful synthesizable syntax only.
7. No compare to an unknown value (x, z)
8. Reset a sequential circuit before it works !
9. Non-synthesizable but powerful verilog syntax could be used in test pattern.